If our design flow were custom scripted, the following settings
would be self-documented in the Makefile.  With the GUI tool flow,
they need to be set by hand for the project.  Pulling up the
top level menu for each portion of the design flow is done by
highlighting it, pulling down the "Process" part of the top menu
bar, and clicking "Properties...".


Implement Design / Process / Properties...
    Translate Properties
        Implementation User Constraints File  ::  ../adctest.ucf
    Map Properties
        Pack I/O Registers/Latches into IOBs  ::  For Inputs and Outputs
    Place & Route Properties
        Place & Route effort Level (Overall)  ::  Highest

Generate Programming File / Process / Properties...
    Configuration options
        UserID Code  ::  0x7702000a
    Startup options
        Start-Up Clock  ::  JTAG Clock


To change the target chip, e.g., from XC2S150 to XC2S200:
    within "Sources in Project", select "xc2s150-5pq208-XST Verilog"
    then in the "Source" part of the tab menu, click "Properties ..."
    and change the Device type.