# srle.pl
# Copyright (C) 2003 Larry Doolittle <larry\@doolittle.boa.org>

# first arg, data width
$n=16;
if ($ARGV[0]>1 && $ARGV[0]<200) { $n=int($ARGV[0]+.5); }
$n1=$n-1;

$aggsrl="srl16x${n}e";       # entity I define

print "// Verilog $aggsrl definition
// No copyright is claimed on this machine-generated code.
// Automatically generated from perl srle.pl $n
// srle.pl is Copyright (C) 2003 Larry Doolittle <larry\@doolittle.boa.org>

// 16 x $n shift register, aggregated from
// $n instances of 16 x 1 Virtex SRL16E shift registers

`timescale 1ns / 1ns

module $aggsrl(Q, A0, A1, A2, A3, CE, CLK, D);
        input A0, A1, A2, A3, CE, CLK;
        input  [$n1:0] D;
        output [$n1:0] Q;
        wire   [$n1:0] Q, D;
";

for ($i=0; $i<$n; $i++) {
	print "	SRL16E d$i(.Q(Q[$i]), .A0(A0), .A1(A1), .A2(A2), .A3(A3),
		.CE(CE), .CLK(CLK), .D(D[$i]));
";}

print "
endmodule
";
