// route_interim.v
// Board-specific routing to pins for Interim system
// $Id$
// Larry Doolittle, LBNL

// llc-suite Copyright (c) 2004, The Regents of the University of
// California, through Lawrence Berkeley National Laboratory (subject
// to receipt of any required approvals from the U.S. Dept. of Energy).
// All rights reserved.

// Your use of this software is pursuant to a "BSD-style" open
// source license agreement, the text of which is in license.txt
// (md5sum a1e0e81c78f6eba050b0e96996f49fd5) that should accompany
// this file.  If the license agreement is not there, or if you
// have questions about the license, please contact Berkeley Lab's
// Technology Transfer Department at TTD@lbl.gov referring to
// "llc-suite (LBNL Ref CR-1988)"

`timescale 1ns / 1ns


module route_interim(
	input  CLK,                 // pin 1
	output clk40,               // interconnect
	input  DAOV,                // pin a
	input  DBOV,                // pin b
	input  DCOV,                // pin c
	input  DDOV,                // pin d
	output daov_,               // interconnect
	output dbov_,               // interconnect
	output dcov_,               // interconnect
	output ddov_,               // interconnect
	output [1:0] lrc_slot,      // interconnect
	input  IL_STAT,             // pin e
	output il_stat_,            // interconnect
	input  power_down,          // interconnect
	output P_DOWN,              // pin f
        input  RF_ON,               // pin w
        output rf_on_,              // interconnect
	input  rf_kill_,            // interconnect
	output RF_KILL,             // pin y
	output SLEEP,               // pin z
	output DIO1,                // pin g
	output DIO2,                // pin h
	output DIO3,                // pin i
	output DIO4,                // pin j
	output DIO6                 // pin k

);

BUFG u1(clk40, CLK);

// nota bene: inversion to un-do that of U702; input signal
// to board is active high, but our pin 173 is active low.
assign rf_on_ = ~RF_ON;

assign daov_ = DAOV;
assign dbov_ = DBOV;
assign dcov_ = DCOV;
assign ddov_ = DDOV;

assign lrc_slot = 2'b00;
assign il_stat_ = IL_STAT;
assign RF_KILL  = rf_kill_;
assign SLEEP    = 0;

assign DIO1 = 0;
assign DIO2 = 0;
assign DIO3 = 0; // has been used for DS1822 testing
assign DIO4 = 0;
assign DIO6 = 0;

endmodule