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Signals index

M
 memory : RAMB4_S4_S4 : reg
 memory : RAMB4_S8_S8 : reg
 muxout_sample : sporty : reg
N
 next_shifter : ds1822_driver : wire
O
 O : BUFG : output
Connects up to:afterburner:u5:clk80 , vxi_if:u3:host_clk 
 old_rf : rf_timer : reg
 outm : history2e : wire
 outsig40 : afterburner : input
Connects up to:llrf_fcm:afterburner:outsig40 
 outsig40 : fdbk_loop : output
Connects up to:llrf_fcm:fdbk_loop:outsig40 
 outsig40 : history2e : input
Connects up to:llrf_fcm:history2e:outsig40 
 outsig40 : llrf_fcm : wire
Connects down to:history2e:history2e:outsig40 , fdbk_loop:fdbk_loop:outsig40 , afterburner:afterburner:outsig40 
 owpd0 : ds1822_driver : reg
 owpd1 : ds1822_driver : reg
 owpd2 : ds1822_driver : reg
 owpd3 : ds1822_driver : reg
 ow_address : ds1822_driver : wire
 ow_in : ds1822_driver : wire
P
 PCI_AD : llrf_fcm : input
Connects down to:vxi_if:vxi_if:PCI_AD 
 PCI_AD : vxi_if : input
Connects up to:llrf_fcm:vxi_if:PCI_AD 
 PCI_INTA_N : llrf_fcm : output
Connects down to:vxi_if:vxi_if:PCI_INTA_N 
 PCI_INTA_N : vxi_if : output
Connects up to:llrf_fcm:vxi_if:PCI_INTA_N 
 phase : dds : reg
Connects down to:cordic:c:phasein 
 phase1 : rf_timer : reg
 phase2 : rf_timer : reg
 phase3 : rf_timer : reg
 phasein : cordic : input
Connects down to:addsub:ax0:control , addsub:ax0:control , addsub:ay0:control , addsub:ay0:control 
Connects up to:dds:c:phase 
 phaseout : cordic : output
 phase_sense_adjust : llrf_fcm : wire
Connects down to:rf_timer:rf_timer:phase_sense_adjust 
 phase_sense_adjust : rf_timer : output
Connects up to:llrf_fcm:rf_timer:phase_sense_adjust 
 PLL_CLK : llrf_fcm : output
Connects down to:sporty:sporty:PLL_CLK 
 PLL_CLK : sporty : output reg
Connects up to:llrf_fcm:sporty:PLL_CLK 
 PLL_DATA : llrf_fcm : output
Connects down to:sporty:sporty:PLL_DATA 
 PLL_DATA : sporty : output reg
Connects up to:llrf_fcm:sporty:PLL_DATA 
 PLL_LE : llrf_fcm : output
Connects down to:sporty:sporty:PLL_LE 
 PLL_LE : sporty : output reg
Connects up to:llrf_fcm:sporty:PLL_LE 
 PLL_MUXOUT : llrf_fcm : input
Connects down to:sporty:sporty:PLL_MUXOUT 
 PLL_MUXOUT : sporty : input
Connects up to:llrf_fcm:sporty:PLL_MUXOUT 
 pll_muxout_ : llrf_fcm : wire
Connects down to:sporty:sporty:pll_muxout_ , status:status:pll_muxout_ 
 pll_muxout_ : sporty : output
Connects up to:llrf_fcm:sporty:pll_muxout_ 
 pll_muxout_ : status : input
Connects up to:llrf_fcm:status:pll_muxout_ 
 pll_unlocked : status : reg
 power_down : llrf_fcm : wire
Connects down to:rf_timer:rf_timer:power_down 
 power_down : rf_timer : output
Connects up to:llrf_fcm:rf_timer:power_down 
 PREPULSE : llrf_fcm : input
Connects down to:route_fcm:route_fcm:PREPULSE 
 PREPULSE : route_fcm : input
Connects up to:llrf_fcm:route_fcm:PREPULSE 
 prev_product : afterburner : reg
 prev_sig_in : afterburner : reg
 pre_save : stopwatch : reg
 prod1 : fdbk_loop : wire
Connects down to:dkcm_bussed:MUL1:product 
 prod2 : fdbk_loop : wire
Connects down to:dkcm_bussed:MUL2:product 
 prod3 : fdbk_loop : wire
Connects down to:dkcm_bussed:MUL3:product 
 product : afterburner : wire
Connects down to:dkcm_bussed:scale:product 
 product : dkcm_bussed : output
Connects up to:fdbk_loop:MUL1:prod1 , fdbk_loop:MUL2:prod2 , fdbk_loop:MUL3:prod3 , afterburner:scale:product 
 pulse_run : rf_timer : wire
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Created:Wed May 19 11:23:18 2004
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